1. Field of the Invention
The present invention relates to a method of forming a landing pad, and more particularly, to a method of forming a landing pad on the drain and source of a MOS transistor.
2. Description of the Prior Art
A memory cell of a dynamic random access memory (DRAM) is formed with a metal oxide semiconductor (MOS) transistor, a capacitor and a node contact. The MOS transistor is used as the pass transistor of the memory cell for controlling the transmission of electric charge. The capacitor is used for storing electric charge to memorize and output data. The node contact is one type of contact plug for electrically connecting the MOS transistor and the capacitor. As the size of semiconductor devices decreases, it becomes increasingly difficult to form the node contact using only an etching and deposition processes. Therefore, in current semiconductor processes, a landing pad and another contact plug are formed at the bottom of the node contact to reduce the difficulty in the formation of the node contact and to ensure the electrical performance of the DRAM.
Please refer to FIG. 1 to FIG. 5. FIG. 1 to FIG. 5 are schematic diagrams for a prior art method of forming a landing pad 29. The prior art method of forming the landing pad 29 is performed on a semiconductor wafer 10, which employs a first photoresist layer 20 and a second photoresist layer 28 to define the positions of a contact plug 27 and the landing pad 29. As shown in FIG. 1, the semiconductor wafer 10 comprises a silicon substrate 12, a first dielectric layer 18 positioned on the silicon substrate 12, and a first photoresist layer 20 positioned on the first dielectric layer 18. Two gates 14, 16 are positioned on the silicon substrate 12 and covered by the first dielectric layer 18, with two spacers 17 positioned around their peripheries respectively. The first photoresist layer 20 comprises an opening 22 extending down to the surface of the first dielectric layer 18 and is positioned between the two gates 14, 16 for defining the position of the contact plug 27.
As shown in FIG. 2, an anisotropic etching process is first performed to vertically remove the first dielectric layer 18 under the opening 22 to form a contact hole 24. Then, a stripping process is performed to remove the first photoresist layer 20 on the dielectric layer 18. Next, as shown in FIG. 3, a polysilicon layer 26 is formed on the semiconductor wafer 10 to fill the contact hole 24. Next, as shown in FIG. 4, a second photoresist layer 28 is formed on a predetermined area of the semiconductor wafer 10 above the contact hole 24 for defining the position of the landing pad 29.
Finally, as shown in FIG. 5, the polysilicon layer 26 not covered by the second photoresist layer 28 is removed and the residual polysilicon layer 26 becomes a conductive layer 26a. After the second photoresist layer 28 is removed, the landing pad 29 is completed. The top of the conductive layer 26a is used as the landing pad 29 and the bottom of the conductive layer 26a is used as the contact plug 27 for electrically connecting the landing pad 29 and the drain/source positioned under the silicon substrate 12.
Please refer to FIG. 6. FIG. 6 is a sectional schematic diagram of a capacitor formed on the landing pad 29 shown in FIG. 5. In DRAM processing, the surface of the semiconductor wafer 10 is usually defined and differentiated as an array area 11 where the memory cells of the DRAM are formed and a periphery area 13 where the periphery circuits are formed. After the gates 14, 16 are formed in the array area 11 and at least one gate 15 is formed in the periphery area 13, the landing pad 29 and a capacitor are formed in the array area 11. Then, an interconnecting process is performed in the array area 11 and the periphery area 13 at the same time for electrically connecting the memory cell and the periphery circuits with external circuitry.
According to the above-mentioned DRAM process, a second dielectric layer 30, a node contact 31, a bottom storage node 32, a third dielectric layer 33 and an upper field plate 34 are sequentially formed after the landing pad 29 is completed in the array area 11. The bottom storage node 32, the third dielectric layer 33 and the upper field plate 34 form a capacitor 39. One of the gates 14, 16, the contact plug 27, the landing pad 29 the node contact 31 and the capacitor 34 form a memory cell 40.
Next, the interconnecting process is performed to form a fourth dielectric layer 35 on the semiconductor wafer 10 followed by an etching process. Therefore, a first groove (not showed) extending down to the upper field plate 34 is formed in the array area 11 as a channel for electrically connecting the memory cell with external circuitry. At the same time, a second groove 38 extending down to the silicon substrate 12 is formed in the periphery area 13 as another channel for electrically connecting the periphery circuits with external circuitry.
In the prior art method, the lithographic process must be performed twice in forming the first photoresist layer 20 and the second photoresist layer 28 to define the position of the landing pad 29. Consequently, the entire process is complicated and difficult to control. In addition, the sequentially formed node contact 31 may electrically interact with a bit line (not shown) within the second dielectric layer 30, leading to a defect.
Furthermore, the landing pad 29 is formed on the first dielectric layer 18 and is electrically connected to the silicon substrate 12 with the contact plug 27 inlayed in the first dielectric layer 18. Consequently, the thickness of the memory cell 40 subsequently formed in the array area 11 will be very large. Therefore, the distance from the surface of the fourth dielectric layer 35 to the surface of the silicon substrate 12 will then be quite long, increasing the difficulty in forming the second groove 38.